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74VHCT74A Dual D-Type Flip-Flop with Preset and Clear
July 1997 Revised February 2005
74VHCT74A Dual D-Type Flip-Flop with Preset and Clear
General Description
The VHCT74A is an advanced high speed CMOS Dual D-Type Flip-Flop fabricated with silicon gate CMOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. The signal level applied to the D INPUT is transferred to the Q OUTPUT during the positive going transition of the CK pulse. CLR and PR are independent of the CK and are accomplished by setting the appropriate input LOW. Protection circuits ensure that 0V to 7V can be applied to the input pins without regard to the supply voltage and to the output pins with VCC 0V. These circuits prevent device destruction due to mismatched supply and input/ output voltages. This device can be used to interface 3V to 5V systems and two supply systems such as battery backup.
Features
s High speed: fMAX
160 MHz (typ) at TA 2.0V, VIL
25qC
s High noise immunity: VIH
0.8V
s Power down protection is provided on all inputs and outputs s Low power dissipation:
ICC
2 PA (max) at TA
25qC
s Pin and function compatible with 74HCT74
Ordering Code:
Order Number 74VHCT74AM 74VHCT74AMX_NL (Note 1) 74VHCT74ASJ 74VHCT74AMTC 74VHCT74AMTCX_NL (Note 1) 74VHCT74AN Package Number M14A M14A M14D MTC14 MTC14 N14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter "X" to the ordering code. Pb-Free package per JEDEC J-STD-020B. Note 1: "_NL" indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
(c) 2005 Fairchild Semiconductor Corporation
DS500026
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74VHCT74A
Logic Symbol
IEEE/IEC
Connection Diagram
Pin Descriptions
Pin Names D1 , D2 CK1, CK2 CLR1, CLR2 PR1, PR2 Q1, Q1, Q2, Q2 Description Data Inputs Clock Pulse Inputs Direct Clear Inputs Direct Preset Inputs Outputs
Truth Table
Inputs CLR L H L H H H PR H L L H H H D X X X L H X CK X X Outputs Function Q L H H L H Qn Q H L H H L Qn No Change Clear Preset

X
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2
74VHCT74A
Absolute Maximum Ratings(Note 2)
Supply Voltage (VCC) DC Input Voltage (VIN) DC Output Voltage (VOUT) (Note 3) (Note 4) Input Diode Current (IIK) Output Diode Current (IOK) (Note 5) DC Output Current (IOUT) DC VCC/GND Current (ICC) Storage Temperature (TSTG) Lead Temperature (TL) Soldering (10 seconds) 260qC
0.5V to 7.0V 0.5V to 7.0V 0.5V to VCC 0.5V 0.5V to 7.0V 20 mA r20 mA r25 mA r50 mA 65qC to 150qC
Recommended Operating Conditions (Note 6)
Supply Voltage (VCC) Input Voltage (VIN) Output Voltage (VOUT) (Note 3) (Note 4) Operating Temperature (TOPR) Input Rise and Fall Time (tr, tf) VCC 5.0V r 0.5V 0 ns/V a 20 ns/V
Note 2: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading varaibles. Fairchild does not recommend operation outside databook specifications. Note 3: HIGH or LOW state. IOUT absolute maximum rating must be observed. Note 4: VCC 0V. Note 5: VOUT GND, V OUT ! VCC.(Outputs Active) Note 6: Unused inputs must be held HIGH or LOW. They may not float.
4.5V to 5.5V 0V to 5.5V 0V to VCC 0V to 5.5V
40qC to 85qC
DC Electrical Characteristics
Symbol VIH VIL VOH VOL IIN ICC ICCT IOFF Parameter HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage LOW Level Output Voltage Input Leakage Current Quiescent Supply Current Maximum ICC/Input Output Leakage Current (Power Down State) VCC (V) 4.5 5.5 4.5 5.5 4.5 4.5 4.5 4.5 0-5.5 5.5 5.5 0.0 4.40 3.94 0.0 0.1 0.36 4.50 Min 2.0 2.0 0.8 0.8 4.40 3.80 0.1 0.44 TA 25qC Typ Max TA
40qC to 85qC
Max 2.0 2.0 0.8 0.8
Min
Units V V V V VIN VIN VIN VIN VIN VOUT
Conditions
VIH VIH
IOH IOL
50 PA 8 mA
50 PA 8 mA
or VIL IOH or VIL IOL
r0.1
2.0 1.35
r1.0
20.0 1.50
PA PA
mA
5.5V or GND VCC or GND 3.4V VCC or GND 5.5V
Other Inputs
0.5
5.0
PA
3
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74VHCT74A
AC Electrical Characteristics
Symbol fMAX tPLH tPHL tPLH tPHL CIN CPD Parameter Maximum Clock Frequency Propagation Delay Time (CK-Q, Q) Propagation Delay time (CLR, PR -Q, Q) Input Capacitance Power Dissipation Capacitance VCC (V) (Note 7) 5.0 5.0 5.0 5.0 5.0 5.0 TA Min 100 80 25qC Typ 160 140 5.8 6.3 7.6 8.1 4 24 7.8 8.8 10.4 11.4 10 Max TA
40qC to 85qC
Max Units CL CL CL CL CL CL VCC Conditions 15 pF 50 pF 15 pF 50 pF 15 pF 50 pF Open
Min 80 65 1.0 1.0 1.0 1.0
MHz 9.0 10.0 12.0 13.0 10 ns ns pF pF
(Note 8)
Note 7: VCC is 5.0 r 0.5V Note 8: CPD is defined as the value of internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC (opr) CPD u VCC u fIN ICC/2 (per flip-flop).
AC Operating Requirements
Symbol tW(L) tW(H) tW(L) tS tH tREM Minimum Pulse Width (CLR, PR) Minimum Setup Time Minimum Hold Time Minimum Removal Time (CLR, PR) Parameter Minimum Pulse Width (CK) VCC (V) 5.0 r 0.5 5.0 r 0.5 5.0 r 0.5 5.0 r 0.5 5.0 r 0.5 Typ TA 25qC TA
40qC to 85qC
Guaranteed Minimum 5.0 5.0 5.0 0 3.5 5.0 5.0 5.0 0 3.5
Units ns ns ns ns ns
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74VHCT74A
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M14A
5
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74VHCT74A
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D
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6
74VHCT74A
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC14
7
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74VHCT74A Dual D-Type Flip-Flop with Preset and Clear
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N14A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 8 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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